noc_fw_l4_per_l4_per_scr Address Map

Module Instance Base Address End Address
noc_fw_l4_per_l4_per_scr 0xFFD13000 0xFFD130FF
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Register Offset Width Access Reset Value Description
nand_register 0x0 32 RW 0x0 
Per-Master Security bit for nand register
nand_data 0x4 32 RW 0x0 
Per-Master Security bit for nand_data
qspi_data 0x8 32 RW 0x0 
Per-Master Security bit for qspi_data
usb0_register 0xC 32 RW 0x0 
Per-Master Security bit for usb0_register
usb1_register 0x10 32 RW 0x0 
Per-Master Security bit for usb1_register
dma_nonsecure 0x14 32 RO 0x1 
Per-Master Security bit for dma_nonsecure
dma_secure 0x18 32 RO 0x0 
Per-Master Security bit for dma_secure
spi_master0 0x1C 32 RW 0x0 
Per-Master Security bit for spi_master0
spi_master1 0x20 32 RW 0x0 
Per-Master Security bit for spi_master1
spi_slave0 0x24 32 RW 0x0 
Per-Master Security bit for spi_slave0
spi_slave1 0x28 32 RW 0x0 
Per-Master Security bit for spi_slave1
emac0 0x2C 32 RW 0x0 
Per-Master Security bit for emac0
emac1 0x30 32 RW 0x0 
Per-Master Security bit for emac1
emac2 0x34 32 RW 0x0 
Per-Master Security bit for emac2
emac3 0x38 32 RO 0x0 
Per-Master Security bit for emac3
qspi 0x3C 32 RW 0x0 
Per-Master Security bit for qspi
sdmmc 0x40 32 RW 0x0 
Per-Master Security bit for sdmmc
gpio0 0x44 32 RW 0x0 
Per-Master Security bit for gpio0
gpio1 0x48 32 RW 0x0 
Per-Master Security bit for gpio1
gpio2 0x4C 32 RW 0x0 
Per-Master Security bit for gpio2
i2c0 0x50 32 RW 0x0 
Per-Master Security bit for i2c0
i2c1 0x54 32 RW 0x0 
Per-Master Security bit for i2c1
i2c2 0x58 32 RW 0x0 
Per-Master Security bit for i2c2
i2c3 0x5C 32 RW 0x0 
Per-Master Security bit for i2c3
i2c4 0x60 32 RW 0x0 
Per-Master Security bit for i2c4
sp_timer0 0x64 32 RW 0x0 
Per-Master Security bit for sp_timer0
sp_timer1 0x68 32 RW 0x0 
Per-Master Security bit for sp_timer1
uart0 0x6C 32 RW 0x0 
Per-Master Security bit for uart0
uart1 0x70 32 RW 0x0 
Per-Master Security bit for uart1