fpga2soc_rate_ad_main_RateAdapter_Bypass

Module Instance	Base Address	Register Address
`i_noc_mpu_m0_fpga2soc_rate_ad_main_RateAdapter`	`0xFFD11400`	`0xFFD1140C`

Offset: 0xC

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`															`BYPASS` `RW 0x0`

fpga2soc_rate_ad_main_RateAdapter_Bypass Fields

Bit	Name	Description	Access	Reset
0	`BYPASS`	Disable the rate adaptation capability. This causes the rate adapter to act as a FIFO by transmitting received words, without delay, as soon as they can be transmitted. This setting is useful when the incoming throughput is equal to or greater than the downstream throughput.	`RW`	`0x0`

Bit

Name

Description

Access

Reset

BYPASS

Disable the rate adaptation capability. This causes the rate adapter to act as a FIFO by transmitting received words, without delay, as soon as they can be transmitted. This setting is useful when the incoming throughput is equal to or greater than the downstream throughput.

RW

0x0