hdsktimeout

         The Warm Reset handshake timeout will default to 10,240 which at 100 MHz for l4_sys_free_clk will 102.4 micro-seconds.  This value will be a 25 bit programmable value in SW.  The reason for this is the HMC adaptor may need a longer time to clear all outstanding SDRAM transactions.  The maximum programmable value would be 20.97 msec

Module Instance	Base Address	Register Address
`i_rst_mgr_rstmgr`	`0xFFD05000`	`0xFFD05064`

Offset: 0x64

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`							`val` `RW 0x2800`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`val` `RW 0x2800`

hdsktimeout Fields

Bit	Name	Description	Access	Reset
24:0	`val`	hand shake timeout	`RW`	`0x2800`