l3warmmask

         The L3WARMMASK register is used by software to mask the assertion of module reset signals for hardware sequenced warm resets. There is a writeable bit for each module reset signal that is asserted by default on a hardware sequenced warm reset. If the bit is 1, the module reset signal is asserted by a hardware sequenced warm reset. If the bit is 0, the module reset signal is not changed by a hardware sequenced warm reset. The bit assignments of the *WARMMASK registers match the corresponding *MODRST registers. Any module reset signals that are never asserted by a warm reset have reserved bit offsets and are tied to 0 (read as 0, writes are ignored).

All fields are only reset by a cold reset.

Note that there is no module reset for the L3 interconnect in any *MODRST register because there would be no way for a master to remove the module reset to the L3 once asserted.

Module Instance	Base Address	Register Address
`i_rst_mgr_rstmgr`	`0xFFD05000`	`0xFFD05058`

Offset: 0x58

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`															`l3` `RW 0x1`

l3warmmask Fields

Bit	Name	Description	Access	Reset
0	`l3`	Masks hardware sequenced warm reset to L3 Interconnect	`RW`	`0x1`