syswarmmask

         The SYSWARMMASK register is used by software to mask the assertion of module reset signals for hardware sequenced warm resets. There is a writeable bit for each module reset signal that is asserted by default on a hardware sequenced warm reset. If the bit is 1, the module reset signal is asserted by a hardware sequenced warm reset. If the bit is 0, the module reset signal is not changed by a hardware sequenced warm reset. The bit assignments of the *WARMMASK registers match the corresponding *MODRST registers. Any module reset signals that are never asserted by a warm reset have reserved bit offsets and are tied to 0 (read as 0, writes are ignored).

All fields are only reset by a cold reset.
Fields in the SYSMODRST register associated with cold reset or debug domain reset aren't present in the MISCWARMMASK register and are reserved.
Module Instance Base Address Register Address
i_rst_mgr_rstmgr 0xFFD05000 0xFFD05050

Offset: 0x50

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

ocramocp

RW 0x1

sysdbg

RW 0x1

s2f

RW 0x1

fpgamgr

RW 0x1

Reserved

ocram

RW 0x1

rom

RW 0x1

syswarmmask Fields

Bit Name Description Access Reset
6 ocramocp 
Masks hardware sequenced warm reset for On-chip RAM ECC OCP Diagnostic module
 RW 0x1
5 sysdbg 
Masks hardware sequenced warm reset for logic that spans the system and debug domains.
 RW 0x1
4 s2f 
Masks hardware sequenced warm reset for logic in FPGA core that doesn't differentiate between HPS cold and warm resets
 RW 0x1
3 fpgamgr 
Masks hardware sequenced warm reset for FPGA Manager
 RW 0x1
1 ocram 
Masks hardware sequenced warm reset for On-chip RAM
 RW 0x1
0 rom 
Masks hardware sequenced warm reset for Boot ROM
 RW 0x1