brgwarmmask

         The Bridge_WARM_MASK register is used by software to mask the assertion of module reset signals for hardware sequenced warm resets. There is a writeable bit for each module reset signal that is asserted by default on a hardware sequenced warm reset. If the bit is 1, the module reset signal is asserted by a hardware sequenced warm reset. If the bit is 0, the module reset signal is not changed by a hardware sequenced warm reset. The bit assignments of the *WARMMASK registers match the corresponding *MODRST registers. Any module reset signals that are never asserted by a warm reset have reserved bit offsets and are tied to 0 (read as 0, writes are ignored).

All fields are only reset by a cold reset.
Module Instance Base Address Register Address
i_rst_mgr_rstmgr 0xFFD05000 0xFFD0504C

Offset: 0x4C

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

ddrsch

RW 0x1

f2ssdram2

RW 0x1

f2ssdram1

RW 0x1

f2ssdram0

RW 0x1

fpga2hps

RW 0x1

lwhps2fpga

RW 0x1

hps2fpga

RW 0x1

brgwarmmask Fields

Bit Name Description Access Reset
6 ddrsch 
Masks hardware sequenced warm reset for the DDR Scheduler in the NOC.
 RW 0x1
5 f2ssdram2 
Masks hardware sequenced warm reset for F2S_SDRAM2 Bridge
 RW 0x1
4 f2ssdram1 
Masks hardware sequenced warm reset for F2S_SDRAM1 Bridge
 RW 0x1
3 f2ssdram0 
Masks hardware sequenced warm reset for F2S_SDRAM0 Bridge
 RW 0x1
2 fpga2hps 
Masks hardware sequenced warm reset for FPGA2HPS Bridge
 RW 0x1
1 lwhps2fpga 
Masks hardware sequenced warm reset for LWHPS2FPGA Bridge
 RW 0x1
0 hps2fpga 
Masks hardware sequenced warm reset for HPS2FPGA Bridge
 RW 0x1