coldmodrst

         The COLDMODRST register is used by software to trigger module resets (individual module reset signals). Software explicitly asserts and de-asserts module reset signals by writing bits in the appropriate *MODRST register. It is up to software to ensure module reset signals are asserted for the appropriate length of time and are de-asserted in the correct order. It is also up to software to not assert a module reset signal that would prevent software from de-asserting the module reset signal. For example, software should not assert the module reset to the CPU executing the software.

Software writes a bit to 1 to assert the module reset signal and to 0 to de-assert the module reset signal.

All fields are only reset by a cold reset

Module Instance	Base Address	Register Address
`i_rst_mgr_rstmgr`	`0xFFD05000`	`0xFFD05034`

Offset: 0x34

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`								`iomgrcold` `RW 0x0`	`hmccold` `RW 0x0`	`tapcold` `RW 0x0`	`timestampcold` `RW 0x0`	`s2fcold` `RW 0x0`	`Reserved`		`clkmgrcold` `RW 0x0`

coldmodrst Fields

Bit	Name	Description	Access	Reset
7	`iomgrcold`	Resets logic in IO Manager that is only reset by a cold reset (ignores warm reset)	`RW`	`0x0`
6	`hmccold`	Resets logic in HMC affected only by a cold reset.	`RW`	`0x0`
5	`tapcold`	Resets portion of DAP JTAG TAP controller no reset by a debug probe reset (i.e. nTRST pin). Cold reset only.	`RW`	`0x0`
4	`timestampcold`	Resets debug timestamp to 0 (cold reset only)	`RW`	`0x0`
3	`s2fcold`	Resets logic in FPGA core that is only reset by a cold reset (ignores warm reset)	`RW`	`0x0`
0	`clkmgrcold`	Resets Clock Manager (cold reset only)	`RW`	`0x0`