sysmodrst

         The SYSMODRST register is used by software to trigger module resets (individual module reset signals). Software explicitly asserts and de-asserts module reset signals by writing bits in the appropriate *MODRST register. It is up to software to ensure module reset signals are asserted for the appropriate length of time and are de-asserted in the correct order. It is also up to software to not assert a module reset signal that would prevent software from de-asserting the module reset signal. For example, software should not assert the module reset to the CPU executing the software.

Software writes a bit to 1 to assert the module reset signal and to 0 to de-assert the module reset signal.

All fields are only reset by a cold reset

Module Instance	Base Address	Register Address
`i_rst_mgr_rstmgr`	`0xFFD05000`	`0xFFD05030`

Offset: 0x30

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`									`ocramocp` `RW 0x0`	`sysdbg` `RW 0x0`	`s2f` `RW 0x0`	`fpgamgr` `RW 0x0`	`Reserved`	`ocram` `RW 0x0`	`rom` `RW 0x0`

sysmodrst Fields

Bit	Name	Description	Access	Reset
6	`ocramocp`	Resets On-chip RAM ECC OCP Diagnostic module	`RW`	`0x0`
5	`sysdbg`	Resets logic that spans the system and debug domains.	`RW`	`0x0`
4	`s2f`	Resets logic in FPGA core that doesn't differentiate between HPS cold and warm resets	`RW`	`0x0`
3	`fpgamgr`	Resets FPGA Manager	`RW`	`0x0`
1	`ocram`	Resets On-chip RAM	`RW`	`0x0`
0	`rom`	Resets Boot ROM	`RW`	`0x0`