counts

         The COUNTS register is used by software to control reset behavior.It includes fields for software to control the behavior of the warm reset and nRST pin.

Fields are only reset by a cold reset.

Module Instance	Base Address	Register Address
`i_rst_mgr_rstmgr`	`0xFFD05000`	`0xFFD0501C`

Offset: 0x1C

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`warmrstcycles` `RW 0x80`								`Reserved`				`nrstcnt` `RW 0x800`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`nrstcnt` `RW 0x800`

counts Fields

Bit	Name	Description	Access	Reset
31:24	`warmrstcycles`	On a warm reset, the Reset Manager releases the reset to the Clock Manager, and then waits for the number of cycles specified in this register before releasing the rest of the hardware controlled resets.	`RW`	`0x80`
19:0	`nrstcnt`	The Reset Manager pulls down the nRST pin on a warm reset for the number of cycles specified in this register. A value of 0x0 is reserved. nRST assertion on a warm reset may be disabled by clearing NRSTWARMMASK.NRSTPINOE.	`RW`	`0x800`

Bit

Name

Description

Access

Reset

31:24

warmrstcycles

On a warm reset, the Reset Manager releases the reset to the Clock Manager, and then waits for the number of cycles specified in this register before releasing the rest of the hardware controlled resets.

RW

0x80

19:0

nrstcnt

The Reset Manager pulls down the nRST pin on a warm reset for the number of cycles specified in this register.  A value of 0x0 is reserved.  nRST assertion on a warm reset may be disabled by clearing NRSTWARMMASK.NRSTPINOE.

RW

0x800