hdskack

         The CTRL register is used by software to control reset behavior.It includes fields for software to initiate the cold and warm reset, enable hardware handshake with other modules before warm reset, and perform software handshake. The software handshake sequence must match the hardware sequence. Software mustde-assert the handshake request after asserting warm reset and before de-assert the warm reset.

Fields are only reset by a cold reset.
Module Instance Base Address Register Address
i_rst_mgr_rstmgr 0xFFD05000 0xFFD05018

Offset: 0x18

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

etrstallwarmrst

RW 0x0

Reserved

etrstallack

RO 0x0

fpgahsack

RO 0x0

fpgamgrhsack

RO 0x0

sdrselfreqack

RO 0x0

hdskack Fields

Bit Name Description Access Reset
8 etrstallwarmrst 
If a warm reset occurs and ETRSTALLEN is 1, hardware sets this bit to 1 to indicate that the stall of the ETR AXI master is pending. Hardware leaves the ETR stalled until software clears this field by writing it with 1. Software must only clear this field when it is ready to have the ETR AXI master start making AXI requests to write trace data.
 RW 0x0
3 etrstallack 
This is the acknowlege for a ETR AXI master stall initiated by the ETRSTALLREQ field.  A 1 indicates that the ETR has stalled its AXI master
 RO 0x0
2 fpgahsack 
This is the acknowlege (high active) that the FPGA handshake   acknowledge has been received by Reset Manager.
 RO 0x0
1 fpgamgrhsack 
This is the acknowlege (high active) that the FPGA manager has successfully idled its output clock.
 RO 0x0
0 sdrselfreqack 
This is the acknowlege for a SDRAM self-refresh mode request initiated by the SDRSELFREFREQ field.  A 1 indicates that the SDRAM Controller Subsystem has put the SDRAM devices into self-refresh mode.
 RO 0x0