miscstat

         The MISCSTAT register contains bits that indicate the timeout event. For timeout events, a field is 1 if its associated timeout occured as part of a hardware sequenced warm/debug reset.

Software clears bits by writing them with a value of 1. Writes to bits with a value of 0 are ignored.

After a cold reset is complete, all bits are reset to their reset value except for the bit(s) that indicate the source of the cold reset. If multiple cold reset requests overlap with each other, the source de-asserts the request last will be logged. The other reset request source(s)  de-assert the request in the same cycle will also be logged, the rest of the fields are reset to default value of 0.

 After a warm reset is complete, the bit(s) that indicate the source of  the warm reset are set to 1. A warm reset doesn't clear any of the bits  in the MISCSTAT register; these bits must be cleared by software writing  the STAT register.
Module Instance Base Address Register Address
i_rst_mgr_rstmgr 0xFFD05000 0xFFD05008

Offset: 0x8

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

etrstalltimeout

RW 0x0

fpgahstimeout

RW 0x0

fpgamgrhstimeout

RW 0x0

sdrselfreftimeout

RW 0x0

miscstat Fields

Bit Name Description Access Reset
3 etrstalltimeout 
A 1 indicates that Reset Manager's request to the ETR (Embedded Trace Router) to stall its AXI master port before starting a hardware sequenced warm reset timed-out and the Reset Manager had to proceed with the warm reset anyway.
 RW 0x0
2 fpgahstimeout 
A 1 indicates that Reset Manager's handshake request to FPGA before starting a hardware sequenced warm reset timed-out and the Reset Manager had to proceed with the warm reset anyway.
 RW 0x0
1 fpgamgrhstimeout 
A 1 indicates that Reset Manager's request to the FPGA manager to stop driving configuration clock to FPGA CB before starting a hardware sequenced warm reset timed-out and the Reset Manager had to proceed with the warm reset anyway.
 RW 0x0
0 sdrselfreftimeout 
A 1 indicates that Reset Manager's request to the SDRAM Controller Subsystem to put the SDRAM devices into self-refresh mode before starting a hardware sequenced warm reset timed-out and the Reset Manager had to proceed with the warm reset anyway.
 RW 0x0