ramstat
The RAMSTAT register contains bits that indicate the security RAM clearing event during cold or warm reset for each RAM.
Software clears bits by writing them with a value of 1. Writes to bits with a value of 0 are ignored.
For MPU, there are seperate bits for L1 invalidate only or full security clearing.
There is another bit for L1 invalidate timeout error only. The security RAM clearing does not have a timeout.
| Module Instance | Base Address | Register Address |
|---|---|---|
| i_rst_mgr_rstmgr | 0xFFD05000 | 0xFFD05004 |
Offset: 0x4
Access: RW
Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Reserved |
mpul1timeout RW 0x0 |
mpul1ramclr RW 0x0 |
|||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
mwpramclr RW 0x0 |
qspiramclr RW 0x0 |
emac2rxramclr RW 0x0 |
emac2txramclr RW 0x0 |
emac1txramclr RW 0x0 |
emac1rxramclr RW 0x0 |
emac0txramclr RW 0x0 |
emac0rxramclr RW 0x0 |
nanderamclr RW 0x0 |
nandrramclr RW 0x0 |
nandwramclr RW 0x0 |
dmaramclr RW 0x0 |
sdmmcramclr RW 0x0 |
otg1ramclr RW 0x0 |
otg0ramclr RW 0x0 |
onchipramclr RW 0x0 |
ramstat Fields
| Bit | Name | Description | Access | Reset |
|---|---|---|---|---|
| 17 | mpul1timeout | RAMSTATUS bit to indicate MPU l1 RAM cleared timeout during cold/warm reset |
RW | 0x0 |
| 16 | mpul1ramclr | RAMSTATUS bit to indicate MPU L1 invalidate clearing only or full security clearing during cold/warm reset |
RW | 0x0 |
| 15 | mwpramclr | RAMSTATUS bit to indicate MWP RAM is cleared during cold/warm reset |
RW | 0x0 |
| 14 | qspiramclr | RAMSTATUS bit to indicate QSPI RAM is cleared during cold/warm reset |
RW | 0x0 |
| 13 | emac2rxramclr | RAMSTATUS bit to indicate EMAC2 RX RAM is cleared during cold/warm reset |
RW | 0x0 |
| 12 | emac2txramclr | RAMSTATUS bit to indicate EMAC2 TX RAM is cleared during cold/warm reset |
RW | 0x0 |
| 11 | emac1txramclr | RAMSTATUS bit to indicate EMAC1 TX RAM is cleared during cold/warm reset |
RW | 0x0 |
| 10 | emac1rxramclr | RAMSTATUS bit to indicate EMAC1 RX RAM is cleared during cold/warm reset |
RW | 0x0 |
| 9 | emac0txramclr | RAMSTATUS bit to indicate EMAC0 TX RAM is cleared during cold/warm reset |
RW | 0x0 |
| 8 | emac0rxramclr | RAMSTATUS bit to indicate EMAC0 RX RAM is cleared during cold/warm reset |
RW | 0x0 |
| 7 | nanderamclr | RAMSTATUS bit to indicate NAND ECC RAM is cleared during cold/warm reset |
RW | 0x0 |
| 6 | nandrramclr | RAMSTATUS bit to indicate NAND Read RAM is cleared during cold/warm reset |
RW | 0x0 |
| 5 | nandwramclr | RAMSTATUS bit to indicate NAND Write RAM is cleared during cold/warm reset |
RW | 0x0 |
| 4 | dmaramclr | RAMSTATUS bit to indicate DMA RAM is cleared during cold/warm reset |
RW | 0x0 |
| 3 | sdmmcramclr | RAMSTATUS bit to indicate SDMMC RAM is cleared during cold/warm reset |
RW | 0x0 |
| 2 | otg1ramclr | RAMSTATUS bit to indicate USB1 RAM is cleared during cold/warm reset |
RW | 0x0 |
| 1 | otg0ramclr | RAMSTATUS bit to indicate USB0 RAM is cleared during cold/warm reset |
RW | 0x0 |
| 0 | onchipramclr | RAMSTATUS bit to indicate Onchip RAM is cleared during cold/warm reset |
RW | 0x0 |