nocclk

         Contains settings that control clock main_clk generated from the Main PLL VCO clock.

Module Instance	Base Address	Register Address
`i_clk_mgr_alteragrp`	`0xFFD04140`	`0xFFD04144`

Offset: 0x4

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`					`pericnt` `RW 0x3`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`					`maincnt` `RW 0x3`

nocclk Fields

Bit	Name	Description	Access	Reset
26:16	`pericnt`	Divides the VCO frequency by the value+1 in this field. This field loads the internal counter in the NOC PLL for the NOC Clock Group.	`RW`	`0x3`
10:0	`maincnt`	Divides the VCO frequency by the value+1 in this field. This field loads the internal counter in the NOC PLL for the NOC Clock Group.	`RW`	`0x3`

Bit

Name

Description

Access

Reset

26:16

pericnt

Divides the VCO frequency by the value+1 in this field.  This field loads the internal counter in the NOC PLL for the NOC Clock Group.

RW

0x3

10:0

maincnt

Divides the VCO frequency by the value+1 in this field.  This field loads the internal counter in the NOC PLL for the NOC Clock Group.

RW

0x3