mpuclk

         Contains internal counter setting for MPU Clock groups for both PLLs.

Module Instance	Base Address	Register Address
`i_clk_mgr_alteragrp`	`0xFFD04140`	`0xFFD04140`

Offset: 0x0

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`					`pericnt` `RW 0x1`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`					`maincnt` `RW 0x1`

mpuclk Fields

Bit	Name	Description	Access	Reset
26:16	`pericnt`	Divides the VCO frequency by the value+1 in this field. This field loads the internal counter in the Main PLL for the Main Clock Group. Note: Intel recommends that you do not alter the value of this register. Changing the value at run time can cause the system to become unstable.	`RW`	`0x1`
10:0	`maincnt`	Divides the VCO frequency by the value+1 in this field. This field loads the internal counter in the Main PLL for the Main Clock Group. Note: Intel recommends that you do not alter the value of this register. Changing the value at run time can cause the system to become unstable.	`RW`	`0x1`