bypass

         Contains fields that control bypass for clocks derived from the Peripheral PLL.
1: The clock is bypassed.
0: The clock is derived from the 5:1 active mux.
      
Module Instance Base Address Register Address
i_clk_mgr_perpllgrp 0xFFD040C0 0xFFD040D4

Offset: 0x14

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

fben

RW 0x1

rfen

RW 0x1

s2fuser1

RW 0x1

sdmmc

RW 0x1

gpiodb

RW 0x1

emacptp

RW 0x1

emacb

RW 0x1

emaca

RW 0x1

bypass Fields

Bit Name Description Access Reset
7 fben
If set, the pll_main_fben_clk will be bypassed to the boot_clk.  The pll_main_fben_clk is used to synchronously update the Numerator to the Main PLL.
RW 0x1
6 rfen
If set, the pll_peri_rfen_clk will be bypassed to the boot_clk.  The pll_peri_rfen_clk is used to synchronously update the Denominator to the Peripheral PLL.
RW 0x1
5 s2fuser1
If set, the s2f_user1_clk will be bypassed to the boot_clk.
RW 0x1
4 sdmmc
If set, the sdmmc_clk will be bypassed to the boot_clk.
RW 0x1
3 gpiodb
If set, the gpio_db_clk will be bypassed to the boot_clk.
RW 0x1
2 emacptp
If set, the emac_ptp_clk will be bypassed to the boot_clk.
RW 0x1
1 emacb
If set, the emacb_free_clk will be bypassed to the boot_clk.
RW 0x1
0 emaca
If set, the emaca_free_clk will be bypassed to the boot_clk.
RW 0x1