nocdiv
Contains fields that control clock dividers for NoC Clocks.
| Module Instance | Base Address | Register Address |
|---|---|---|
| i_clk_mgr_mainpllgrp | 0xFFD04040 | 0xFFD040A8 |
Offset: 0x68
Access: RW
Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Reserved |
cspdbgclk RW 0x1 |
cstraceclk RW 0x2 |
csatclk RW 0x0 |
Reserved |
l4spclk RW 0x2 |
||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved |
l4mpclk RW 0x1 |
Reserved |
l4mainclk RW 0x0 |
||||||||||||
nocdiv Fields
| Bit | Name | Description | Access | Reset | ||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 28 | cspdbgclk | The external cs_pdbg_clk divider is specified in this field. This divider is cascaded after the cs_at_clk external divider.
|
RW | 0x1 | ||||||||||
| 27:26 | cstraceclk | The external cs_trace_clk divider is specified in this field. The cs_trace_clk is used by the actual trace interface to the debugger. This divider is cascaded after the cs_at_clk external divider.
|
RW | 0x2 | ||||||||||
| 25:24 | csatclk | The external cs_at_clk divider is specified in this field.
|
RW | 0x0 | ||||||||||
| 17:16 | l4spclk | The external l4_sp_clk divider is specified in this field.
|
RW | 0x2 | ||||||||||
| 9:8 | l4mpclk | The external l4_mp_clk divider is specified in this field.
|
RW | 0x1 | ||||||||||
| 1:0 | l4mainclk | The external l4_main_clk divider is specified in this field.
|
RW | 0x0 |