outrst

         Contains settings to assert individual Outreset for all Main PLL Counters.
      
Module Instance Base Address Register Address
i_clk_mgr_mainpllgrp 0xFFD04040 0xFFD040A0

Offset: 0x60

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

outreset

RW 0x0

outrst Fields

Bit Name Description Access Reset
15:0 outreset
Resets the individual PLL output counter.
For software to change the PLL output counter without producing glitches on the respective clock, SW must set the Output Counter Reset Register 'Output Counter Reset' bit. Software then polls the respective Output Counter Reset Acknowledge bit in the Output Counter Reset Ack Status Register. Software then writes the appropriate counter register, and then clears the respective Output Counter Reset bit.
LSB 'outreset[0]' corresponds to PLL output clock C0, etc.
If set to '1', reset output divider, no clock output from counter.
If set to '0', counter is not reset.
The reset value of this bit is applied on a cold reset; warm reset has no affect on this bit.
RW 0x0