vco0

Module Instance	Base Address	Register Address
`i_clk_mgr_mainpllgrp`	`0xFFD04040`	`0xFFD04040`

Offset: 0x0

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`			`bwadjen` `RW 0x0`	`bwadj` `RW 0x1`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`						`psrc` `RW 0x0`		`Reserved`	`saten` `RW 0x1`	`fasten` `RW 0x0`	`regextsel` `RW 0x0`	`outresetall` `RW 0x0`	`en` `RW 0x0`	`pwrdn` `RW 0x1`	`bgpwrdn` `RW 0x1`

vco0 Fields

Bit

Name

Description

Access

Reset

bwadjen

If set to 1, the Loop Bandwidth Adjust value comes from the Loop Bandwidth Adjust field.
If set to 0, the Loop Bandwidth Adjust value equals the M field divided by 2 value of the VCO Control Register.  The M divided by 2 is the upper 12 bits (12:1) of the M field in the VCO register.

RW

0x0

27:16

bwadj

Provides Loop Bandwidth Adjust value.

RW

0x1

9:8

psrc

Controls the VCO input clock source.

Value	Description
0	HPS_CLK1 (external oscillator input pin). Internal signal within device is named osc1_clk.
1	cb_intosc_ls_clk (internal low speed oscillator)
2	f2h_free_clk (FPGA fabric PLL clock reference)

RW

0x0

saten

Enables saturation behavior.

RW

0x1

fasten

Enables fast locking circuit.

RW

0x0

regextsel

If set to '1', the external regulator is selected for the PLL.
If set to '0', the internal regulator is slected.
It is strongly recommended to select the external regulator while the PLL is not enabled (in reset), and  then disable the external regulater once the PLL becomes enabled.  Software should simulateously update the 'Enable' bit and the 'External Regulator Input Select' in the same write access to the VCO register.  When the 'Enable' bit is clear, the 'External Regulator Input Select' should be set, and vice versa.
The reset value of this bit is applied on a cold reset; warm reset has no affect on this bit.

RW

0x0

outresetall

Before releasing Bypass, All Output Counter Reset must be set and cleared by software for correct clock operation.
If '1', Reset phase multiplexer and all output counter state. So that after the assertion all the clocks output are start from rising edge align.
If '0', phase multiplexer and output counter state not reset and no change to the phase of the clock outputs.

RW

0x0

en

If '1', VCO is enabled. If '0', VCO is in reset.

RW

0x0

pwrdn

If '1', power down analog circuitry. If '0', analog circuitry not powered down.

RW

0x1

bgpwrdn

If '1', powers down bandgap. If '0', bandgap is not power down.

RW

0x1