wdt_comp_param_1

         Component Parameters Register 1
      
Module Instance Base Address Register Address
i_watchdog_0_l4wd 0xFFD00200 0xFFD002F4
i_watchdog_1_l4wd 0xFFD00300 0xFFD003F4

Offset: 0xF4

Access: RO

Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

rsvd_31_29

RO 0x0

cp_wdt_cnt_width

RO 0x10

cp_wdt_dflt_top_init

RO 0xF

cp_wdt_dflt_top

RO 0xF

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

rsvd_15_13

RO 0x0

cp_wdt_dflt_rpl

RO 0x0

cp_wdt_apb_data_width

RO 0x2

cp_wdt_pause

RO 0x0

cp_wdt_use_fix_top

RO 0x1

cp_wdt_hc_top

RO 0x0

cp_wdt_hc_rpl

RO 0x1

cp_wdt_hc_rmod

RO 0x0

cp_wdt_dual_top

RO 0x1

cp_wdt_dflt_rmod

RO 0x0

cp_wdt_always_en

RO 0x0

wdt_comp_param_1 Fields

Bit Name Description Access Reset
31:29 rsvd_31_29

RO 0x0
28:24 cp_wdt_cnt_width

Value Description
0x10 WIDTH32BITS
RO 0x10
23:20 cp_wdt_dflt_top_init

Value Description
0xf TIMEOUT15
RO 0xF
19:16 cp_wdt_dflt_top

Value Description
0xf TIMEOUT15
RO 0xF
15:13 rsvd_15_13

RO 0x0
12:10 cp_wdt_dflt_rpl

Value Description
0x0 PULSE2CYCLES
RO 0x0
9:8 cp_wdt_apb_data_width

Value Description
0x2 WIDTH32BITS
RO 0x2
7 cp_wdt_pause

RO 0x0
6 cp_wdt_use_fix_top

Value Description
0x1 PREDEFINED
RO 0x1
5 cp_wdt_hc_top

Value Description
0x0 PROGRAMMABLE
RO 0x0
4 cp_wdt_hc_rpl

Value Description
0x1 HARDCODED
RO 0x1
3 cp_wdt_hc_rmod

Value Description
0x0 PROGRAMMABLE
RO 0x0
2 cp_wdt_dual_top

Value Description
0x1 DUALTOP
RO 0x1
1 cp_wdt_dflt_rmod

Value Description
0x0 RSTREQ
RO 0x0
0 cp_wdt_always_en

Value Description
0x0 DISABLED
RO 0x0