wdt_cr
Control Register
| Module Instance | Base Address | Register Address |
|---|---|---|
| i_watchdog_0_l4wd | 0xFFD00200 | 0xFFD00200 |
| i_watchdog_1_l4wd | 0xFFD00300 | 0xFFD00300 |
Offset: 0x0
Access: RW
Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Reserved |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved |
rpl RO 0x0 |
rmod RW 0x0 |
wdt_en RW 0x0 |
||||||||||||
wdt_cr Fields
| Bit | Name | Description | Access | Reset | ||||||
|---|---|---|---|---|---|---|---|---|---|---|
| 4:2 | rpl | Reset pulse length.This field identifies the number of pclk cycles for which the system reset stays asserted. 000 - 2 pclk cycles 001 - 4 pclk cycles 010 - 8 pclk cycles 011 - 16 pclk cycles 100 - 32 pclk cycles 101 - 64 pclk cycles 110 - 128 pclk cycles 111 - 256 pclk cycles |
RO | 0x0 | ||||||
| 1 | rmod | Response mode.
Selects the output response generated to a timeout.
0 = Generate a system reset.
1 = First generate an interrupt and if it is not cleared by the time
a second timeout occurs then generate a system reset.
|
RW | 0x0 | ||||||
| 0 | wdt_en | WDT enable. Writable when the configuration parameter WDT_ALWAYS_EN = 0, otherwise, it is readable. This bit is used to enable and disable the DW_apb_wdt. When disabled, the counter does not decrement. Thus, no interrupts or system resets are generated. Once this bit has been enabled, it can be cleared only by a system reset. 0 = WDT disabled. 1 = WDT enabled.
|
RW | 0x0 |