timersrawintstat
Name: Timers Raw Interrupt Status Register
Size: 1-9 bits
Address Offset: 0xa8
Read/Write Access: Read
| Module Instance | Base Address | Register Address |
|---|---|---|
| i_timer_sys_0_timer | 0xFFD00000 | 0xFFD000A8 |
| i_timer_sys_1_timer | 0xFFD00100 | 0xFFD001A8 |
Offset: 0xA8
Access: RO
Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Reserved |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved |
timersrawintstat RO 0x0 |
||||||||||||||
timersrawintstat Fields
| Bit | Name | Description | Access | Reset | ||||||
|---|---|---|---|---|---|---|---|---|---|---|
| 0 | timersrawintstat | The register contains the unmasked interrupt status of all timers in the component. 0 = either timer_intr or timer_intr_n is not active prior to masking 1 = either timer_intr or timer_intr_n is active prior to masking.
|
RO | 0x0 |