ECC_REG2RDDATABUS_BEAT3

         ECC Reg2Rddatabus_beat3
Module Instance Base Address Register Address
ecc_hmc_ocp_slv_block 0xFFCFB000 0xFFCFB17C

Offset: 0x17C

Access: RW

Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

ECC3BUS

0x0

ECC2BUS

0x0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ECC1BUS

0x0

ECC0BUS

0x0

ECC_REG2RDDATABUS_BEAT3 Fields

Bit Name Description Access Reset
31:24 ECC3BUS 
Data ECC from the register will be written to the RAM. 
Based on the DDR IO width, unimplemented bytes of this register will read as zero. 
Each (reg2rddatabus_beat[3:0]) register will be shifted in every beat cycle
When data is 16 bit wide: Data ECC is associated with data[255:240].
 RW 0x0
23:16 ECC2BUS 
Data ECC from the register will be written to the RAM. 
Based on the DDR IO width, unimplemented bytes of this register will read as zero.
When data is 16 bit wide: Data ECC is associated with data[191:176].
 RW 0x0
15:8 ECC1BUS 
Data ECC from the register will be written to the RAM. 
Based on the DDR IO width, unimplemented bytes of this register will read as zero.
When data is 16 bit wide: Data ECC is associated with data[127:112].
 RW 0x0
7:0 ECC0BUS 
Data ECC from the register will be written to the RAM
Based on the DDR IO width, unimplemented bytes of this register will read as zero.
When data is 16 bit wide: Data ECC is associated with data[63:48].
 RW 0x0