ECC_RDECCDATA2REGBUS

         ECC of data from RAM will be written to register
Module Instance Base Address Register Address
ecc_hmc_ocp_slv_block 0xFFCFB000 0xFFCFB148

Offset: 0x148

Access: RO

Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

ECC3BUS

0x0

ECC2BUS

0x0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ECC1BUS

0x0

ECC0BUS

0x0

ECC_RDECCDATA2REGBUS Fields

Bit Name Description Access Reset
31:24 ECC3BUS 
ECC of data [255:192] from RAM which will be written to register.
Based on the DDR IO width, unimplemented bytes of this register will read as zero.
 RO 0x0
23:16 ECC2BUS 
ECC of data [191:128] from RAM which will be written to register.
Based on the DDR IO width, unimplemented bytes of this register will read as zero.
 RO 0x0
15:8 ECC1BUS 
ECC of data [127:64] from RAM which will be written to register.
Based on the DDR IO width, unimplemented bytes of this register will read as zero.
 RO 0x0
7:0 ECC0BUS 
ECC of data [63:0] from RAM which will be written to register.
Based on the DDR IO width, unimplemented bytes of this register will read as zero.
 RO 0x0