SERRADDRA

         Single-bit error address

Module Instance	Base Address	Register Address
`ecc_hmc_ocp_slv_block`	`0xFFCFB000`	`0xFFCFB130`

Offset: 0x130

Access: RO

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`SADDRESS` `0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`SADDRESS` `0x0`

SERRADDRA Fields

Bit	Name	Description	Access	Reset
31:0	`SADDRESS`	Last single-bit error address at 256-bit boundary. This register shows the address of the current single-bit error. This address is logged when a new serr_req is generated to the system. This is gated by the single-bit error interrupt enable and ecc_en.	`RO`	`0x0`

Bit

Name

Description

Access

Reset

31:0

SADDRESS

Last single-bit error address at 256-bit boundary.
This register shows the address of the current single-bit error. This address is logged when a new serr_req is generated to the system. This is gated by the single-bit error interrupt enable and ecc_en.

RO

0x0