MODSTAT

         Counter feature status flag

Module Instance	Base Address	Register Address
`ecc_hmc_ocp_slv_block`	`0xFFCFB000`	`0xFFCFB128`

Offset: 0x128

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`							`AUTOWB_DROP_FLG` `0x0`	`Reserved`							`CMPFLGA` `0x0`

MODSTAT Fields

Bit	Name	Description	Access	Reset
8	`AUTOWB_DROP_FLG`	Auto writeback counter match flag. This bit indicates that the internal autoWB counter and autoWB_drop_cnt value matched. 1'b0: read indicates match check of hmi_intr interrupt on compare match is disabled. 1'b1: read indicates compare has matched. Write of one will clear the pending compare match. This will not de-assert the hmi_intr signal - software needs to write to hmi_intrpen bit to clear the interrupt. When the match occurs, additional errors will not increment count until the compare status flag is cleared. If the software does not change the autoWB_drop_cnt register prior to clearing this flag or reset the autoWB counter, next increment of internal autoWB counter could set this flag in the next cycle.	`RW`	`0x0`
0	`CMPFLGA`	Counter Match occurred flag. This bit indicates that the internal counter and SERRCNT value matched. 1'b0: read indicates match check of SERR interrupt on compare match is disabled. 1'b1: read indicates compare has matched. Write of one will clear the pending compare match. This will not de-assert the serr_req signal - software needs to write to serrpen bit to clear the interrupt. When the match occurs, additional errors will not increment count until the compare status flag is cleared. If the software does not change the SERRCNT register prior to clearing this flag or reset the internal counter, next increment of internal counter could set this flag again in the next cycle.	`RW`	`0x0`

Bit

Name

Description

Access

Reset

AUTOWB_DROP_FLG

Auto writeback counter match flag.
This bit indicates that the internal autoWB counter and autoWB_drop_cnt value matched.  
1'b0: read indicates match check of hmi_intr interrupt on compare match is disabled. 
1'b1: read indicates compare has matched.  Write of one will clear the pending compare match. This will not de-assert the hmi_intr signal - software needs to write to hmi_intrpen bit to clear the interrupt. 
When the match occurs, additional errors will not increment count until the compare status flag is cleared. If the software does not change the autoWB_drop_cnt register prior to clearing this flag or reset the autoWB counter, next increment of internal autoWB counter could set this flag in the next cycle.

RW

0x0

CMPFLGA

Counter Match occurred flag.
This bit indicates that the internal counter and SERRCNT value matched.  
1'b0: read indicates match check of SERR interrupt on compare match is disabled. 
1'b1: read indicates compare has matched.  Write of one will clear the pending compare match. This will not de-assert the serr_req signal - software needs to write to serrpen bit to clear the interrupt. 
When the match occurs, additional errors will not increment count until the compare status flag is cleared. If the software does not change the SERRCNT register prior to clearing this flag or reset the internal counter, next increment of internal counter could set this flag again in the next cycle.

RW

0x0