INTMODE

         Interrupt mode

Module Instance	Base Address	Register Address
`ecc_hmc_ocp_slv_block`	`0xFFCFB000`	`0xFFCFB11C`

Offset: 0x11C

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`							`AFICAL_EN` `0x0`	`Reserved`							`INTONCMP` `0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`							`EXT_ADDRPARITY_EN` `0x0`	`Reserved`							`INTMODE` `0x0`

INTMODE Fields

Bit	Name	Description	Access	Reset
24	`AFICAL_EN`	Enable interrupt of memory interface calibration success. This bit is used to enable interrupt of memory interrupt calibration success. The hmi_intr signal will be asserted on a match. 1'b0: HMI interrupts on compare match is disabled. 1'b1: HMI interrupts on compare matched is enabled.	`RW`	`0x0`
16	`INTONCMP`	Enable interrupt on compare match. This bit is used to enable interrupt when the internal counter and SERRCNTA value matches. serr_req signal will be asserted on a match. 1'b0: SERR interrupt on compare match is disabled 1'b1: SERR interrupt on compare match is enabled	`RW`	`0x0`
8	`EXT_ADDRPARITY_EN`	Enable address parity for DDR4 memories. This bit is used to enable the interrupt that generate externally when address parity is detected. when enabled, this will be generating derr_req signal 1'b0: disable address parity on DERR interrupt 1'b1: enable address parity on DERR interrupt	`RW`	`0x0`
0	`INTMODE`	Interrupt mode for single-bit error.This is disabled when SERRINTEN is disabled in the ERRINTEN register. 1'b0: interrupt disbaled 1'b1: generate interrupt on every SERR	`RW`	`0x0`