ECCCTRL1

         ECC control 1.
This bit is used to set the initialize the memory and ecc to a known value

Module Instance	Base Address	Register Address
`ecc_hmc_ocp_slv_block`	`0xFFCFB000`	`0xFFCFB100`

Offset: 0x100

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`															`AUTOWB_CNT_RST` `0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`							`CNT_RST` `0x0`	`Reserved`							`ECC_EN` `0x0`

ECCCTRL1 Fields

Bit	Name	Description	Access	Reset
16	`AUTOWB_CNT_RST`	Reset the auto-write back internal counter to zero. The auto-write back counter is reset to zero when the INTONCMP bit in the INTMODE register is set. 1'b0 : No effect on auto-write back internal counter. Default value after reset 1'b1 : Reset the auto-write back internal counter to zero	`RW`	`0x0`
8	`CNT_RST`	Reset of internal counter. The internal counter is reset to zero when the INTONCMP bit in the INTMODE register is set. 1'b0: No effect on internal counter. Dafault value after reset 1'b1: Reset the internal counter to zero	`RW`	`0x0`
0	`ECC_EN`	Enable for the ECC detection and correction logic. This bit is used to detect and correct any errors within RAM during memory access. 1'b0:ECC block is disabled. Default value after reset. 1'b1: ECC block is enabled. Every RAM access will verify the data and generate any necessary error requests.	`RW`	`0x0`

Bit

Name

Description

Access

Reset

AUTOWB_CNT_RST

Reset the auto-write back internal counter to zero.  The auto-write back counter
is reset to zero when the INTONCMP bit in the INTMODE register is set.
1'b0 : No effect on auto-write back internal counter. Default value after reset
1'b1 :  Reset the auto-write back internal counter to zero

RW

0x0

CNT_RST

Reset of internal counter.  The internal counter is reset to zero when the INTONCMP bit in the
INTMODE register is set.
1'b0: No effect on internal counter. Dafault value after reset
1'b1: Reset the internal counter to zero

RW

0x0

ECC_EN

Enable for the ECC detection and correction logic.  This bit is used to detect and correct
any errors within RAM during memory access.
1'b0:ECC block is disabled. Default value after reset.
1'b1: ECC block is enabled. Every RAM access will verify the data and generate any necessary error requests.

RW

0x0