DDRCALSTAT

         DDR Calibration Register

Module Instance	Base Address	Register Address
`ecc_hmc_ocp_slv_block`	`0xFFCFB000`	`0xFFCFB00C`

Offset: 0xC

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`															`CAL` `0x0`

DDRCALSTAT Fields

Bit	Name	Description	Access	Reset
0	`CAL`	DDR calibration status. This field indicates the calibration status of the hard memory controller's I/O column. During this time the DDR memory is not available. 0x0: When clear, calibration is either on going, hasn't started or failed. 0x1: When set to 1, calibration has succeeded.	`RO`	`0x0`

Bit

Name

Description

Access

Reset

CAL

DDR calibration status.
This field indicates the calibration status of the hard memory controller's I/O column.
During this time the DDR memory is not available.
0x0: When clear, calibration is either on going, hasn't started or failed.
0x1: When set to 1, calibration has succeeded.

RO

0x0