gpio_ls_sync
Name: Synchronization level
Size: 1 bit
Address Offset: 0x60
Read/Write Access: Read/Write
| Module Instance | Base Address | Register Address |
|---|---|---|
| i_gpio_0_gpio | 0xFFC02900 | 0xFFC02960 |
| i_gpio_1_gpio | 0xFFC02A00 | 0xFFC02A60 |
| i_gpio_2_gpio | 0xFFC02B00 | 0xFFC02B60 |
Offset: 0x60
Access: RW
Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Reserved |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved |
gpio_ls_sync RW 0x0 |
||||||||||||||
gpio_ls_sync Fields
| Bit | Name | Description | Access | Reset | ||||||
|---|---|---|---|---|---|---|---|---|---|---|
| 0 | gpio_ls_sync | Writing a 1 to this register results in all level-sensitive interrupts being synchronized to pclk_intr. 0 No synchronization to pclk_intr (default) 1 Synchronize to pclk_intr
|
RW | 0x0 |