doeptsiz12

         Device OUT Endpoint 12 Transfer Size Register

Module Instance	Base Address	Register Address
`i_usbotg_0_devgrp`	`0xFFB00800`	`0xFFB00C90`
`i_usbotg_1_devgrp`	`0xFFB40800`	`0xFFB40C90`

Offset: 0x490

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`	`rxdpid` `RO 0x0`		`pktcnt` `RW 0x0`										`xfersize` `RW 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`xfersize` `RW 0x0`

doeptsiz12 Fields

Bit

Name

Description

Access

Reset

30:29

rxdpid

 Applies to isochronous OUT endpoints only.
This is the data PID received in the last packet for this endpoint.
 2'b00: DATA0
 2'b01: DATA2
 2'b10: DATA1
 2'b11: MDATA
 
SETUP Packet Count (SUPCnt)
Applies to control OUT Endpoints only.
This field specifies the number of back-to-back SETUP data
packets the endpoint can receive.
 2'b01: 1 packet
 2'b10: 2 packets
 2'b11: 3 packets

Value	Description
0x0	DATA0
0x1	DATA2PACKET1
0x2	DATA1PACKET2
0x3	MDATAPACKET3

RO

0x0

28:19

pktcnt

Packet Count (PktCnt)
This field is decremented to zero after a packet is written into the
RxFIFO.

RW

0x0

18:0

xfersize

Transfer Size (XferSize)
Indicates the transfer size in bytes For endpoint 0. The core
interrupts the application only after it has exhausted the transfer
size amount of data. The transfer size can be Set to the
maximum packet size of the endpoint, to be interrupted at the
end of each packet.
The core decrements this field every time a packet is read from
the RxFIFO and written to the external memory.

RW

0x0