doepctl0
Device Control OUT Endpoint 0 Control Register
| Module Instance | Base Address | Register Address |
|---|---|---|
| i_usbotg_0_devgrp | 0xFFB00800 | 0xFFB00B00 |
| i_usbotg_1_devgrp | 0xFFB40800 | 0xFFB40B00 |
Offset: 0x300
Access: RW
Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
epena RW 0x0 |
epdis RO 0x0 |
Reserved |
snak WO 0x0 |
cnak WO 0x0 |
Reserved |
stall RW 0x0 |
snp RW 0x0 |
eptype RO 0x0 |
naksts RO 0x0 |
Reserved |
|||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
usbactep RO 0x1 |
Reserved |
mps RO 0x0 |
|||||||||||||
doepctl0 Fields
| Bit | Name | Description | Access | Reset | ||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | epena | Endpoint Enable (EPEna) When Scatter/Gather DMA mode is enabled, For OUT endpoints this bit indicates that the descriptor structure and data buffer to receive data is setup. When Scatter/Gather DMA mode is disabled(such as For buffer-pointer based DMA mode)this bit indicates that the application has allocated the memory to start receiving data from the USB. The core clears this bit before setting any of the following interrupts on this endpoint: SETUP Phase Done Endpoint Disabled Transfer Completed Note: In DMA mode, this bit must be Set For the core to transfer SETUP data packets into memory.
|
RW | 0x0 | ||||||||||
| 30 | epdis | Endpoint Disable (EPDis) The application cannot disable control OUT endpoint 0.
|
RO | 0x0 | ||||||||||
| 27 | snak | Set NAK (SNAK) A write to this bit sets the NAK bit For the endpoint. Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also Set bit on a Transfer Completed interrupt, or after a SETUP is received on the endpoint.
|
WO | 0x0 | ||||||||||
| 26 | cnak | Clear NAK (CNAK) A write to this bit clears the NAK bit For the endpoint.
|
WO | 0x0 | ||||||||||
| 21 | stall | STALL Handshake (Stall) The application can only Set this bit, and the core clears it, when a SETUP token is received For this endpoint. If a NAK bit or Global OUT NAK is Set along with this bit, the STALL bit takes priority. Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.
|
RW | 0x0 | ||||||||||
| 20 | snp | Snoop Mode (Snp) This bit configures the endpoint to Snoop mode. In Snoop mode, the core does not check the correctness of OUT packets before transferring them to application memory.
|
RW | 0x0 | ||||||||||
| 19:18 | eptype | Endpoint Type (EPType) Hardcoded to 2'b00 For control.
|
RO | 0x0 | ||||||||||
| 17 | naksts | NAK Status (NAKSts) Indicates the following: 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status. 1'b1: The core is transmitting NAK handshakes on this endpoint. When either the application or the core sets this bit, the core stops receiving data, even If there is space in the RxFIFO to accommodate the incoming packet. Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.
|
RO | 0x0 | ||||||||||
| 15 | usbactep | USB Active Endpoint (USBActEP) This bit is always Set to 1, indicating that a control endpoint 0 is always active in all configurations and interfaces.
|
RO | 0x1 | ||||||||||
| 1:0 | mps | Maximum Packet Size (MPS) The maximum packet size For control OUT endpoint 0 is the same as what is programmed in control IN Endpoint 0. 2'b00: 64 bytes 2'b01: 32 bytes 2'b10: 16 bytes 2'b11: 8 bytes
|
RO | 0x0 |