dvbuspulse

         Device VBUS Pulsing Time Register

Module Instance	Base Address	Register Address
`i_usbotg_0_devgrp`	`0xFFB00800`	`0xFFB0082C`
`i_usbotg_1_devgrp`	`0xFFB40800`	`0xFFB4082C`

Offset: 0x2C

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`				`dvbuspulse` `RW 0x5B8`

dvbuspulse Fields

Bit	Name	Description	Access	Reset
11:0	`dvbuspulse`	Device VBUS Pulsing Time (DVBUSPulse) Specifies the VBUS pulsing time during SRP. This value equals: VBUS pulsing time in PHY clocks / 1, 024 The value you use depends whether the PHY is operating at 30 MHz (16-bit data width) or 60 MHz (8-bit data width).	`RW`	`0x5B8`

Bit

Name

Description

Access

Reset

11:0

dvbuspulse

Device VBUS Pulsing Time (DVBUSPulse)
Specifies the VBUS pulsing time during SRP. This value equals:
VBUS pulsing time in PHY clocks / 1, 024
The value you use depends whether the PHY is operating at 30
MHz (16-bit data width) or 60 MHz (8-bit data width).

RW

0x5B8