dvbusdis

         Device VBUS Discharge Time Register

Module Instance	Base Address	Register Address
`i_usbotg_0_devgrp`	`0xFFB00800`	`0xFFB00828`
`i_usbotg_1_devgrp`	`0xFFB40800`	`0xFFB40828`

Offset: 0x28

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`dvbusdis` `RW 0x17D7`

dvbusdis Fields

Bit	Name	Description	Access	Reset
15:0	`dvbusdis`	Device VBUS Discharge Time (DVBUSDis) Specifies the VBUS discharge time after VBUS pulsing during SRP. This value equals: VBUS discharge time in PHY clocks / 1, 024 The value you use depends whether the PHY is operating at 30 MHz (16-bit data width) or 60 MHz (8-bit data width). Depending on your VBUS load, this value can need adjustment.	`RW`	`0x17D7`

Bit

Name

Description

Access

Reset

15:0

dvbusdis

Device VBUS Discharge Time (DVBUSDis)
Specifies the VBUS discharge time after VBUS pulsing during
SRP. This value equals:
VBUS discharge time in PHY clocks / 1, 024
The value you use depends whether the PHY is operating at
30 MHz (16-bit data width) or 60 MHz (8-bit data width).
Depending on your VBUS load, this value can need
adjustment.

RW

0x17D7