hcintmsk10
Host Channel 10 Interrupt Mask Register
| Module Instance | Base Address | Register Address |
|---|---|---|
| i_usbotg_0_hostgrp | 0xFFB00400 | 0xFFB0064C |
| i_usbotg_1_hostgrp | 0xFFB40400 | 0xFFB4064C |
Offset: 0x24C
Access: RW
Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Reserved |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved |
frm_lst_rollintrmsk RW 0x0 |
Reserved |
bnaintrmsk RW 0x0 |
datatglerrmsk RW 0x0 |
frmovrunmsk RW 0x0 |
bblerrmsk RW 0x0 |
xacterrmsk RW 0x0 |
nyetmsk RW 0x0 |
ackmsk RW 0x0 |
nakmsk RW 0x0 |
stallmsk RW 0x0 |
ahberrmsk RW 0x0 |
chhltdmsk RW 0x0 |
xfercomplmsk RW 0x0 |
|
hcintmsk10 Fields
| Bit | Name | Description | Access | Reset | ||||||
|---|---|---|---|---|---|---|---|---|---|---|
| 13 | frm_lst_rollintrmsk | Framelist rollover interrupt Mask register(FRM_LST_ROLLIntrMsk) This bit is valid only when Scatter/Gather DMA mode is enabled.
|
RW | 0x0 | ||||||
| 11 | bnaintrmsk | BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk) This bit is valid only when Scatter/Gather DMA mode is enabled.
|
RW | 0x0 | ||||||
| 10 | datatglerrmsk | Data Toggle Error Mask (DataTglErrMsk) In scatter/gather DMA mode for host, interrupts will not be generated due to the corresponding bits set in HCINTn. |
RW | 0x0 | ||||||
| 9 | frmovrunmsk | Frame Overrun Mask (FrmOvrunMsk) In scatter/gather DMA mode for host, interrupts will not be generated due to the corresponding bits set in HCINTn. |
RW | 0x0 | ||||||
| 8 | bblerrmsk | Babble Error Mask (BblErrMsk) In scatter/gather DMA mode for host, interrupts will not be generated due to the corresponding bits set in HCINTn. |
RW | 0x0 | ||||||
| 7 | xacterrmsk | Transaction Error Mask (XactErrMsk) In scatter/gather DMA mode for host, interrupts will not be generated due to the corresponding bits set in HCINTn. |
RW | 0x0 | ||||||
| 6 | nyetmsk | NYET Response Received Interrupt Mask (NyetMsk) In scatter/gather DMA mode for host, interrupts will not be generated due to the corresponding bits set in HCINTn. |
RW | 0x0 | ||||||
| 5 | ackmsk | ACK Response Received/Transmitted Interrupt Mask (AckMsk) In scatter/gather DMA mode for host, interrupts will not be generated due to the corresponding bits set in HCINTn. |
RW | 0x0 | ||||||
| 4 | nakmsk | NAK Response Received Interrupt Mask (NakMsk) In scatter/gather DMA mode for host, interrupts will not be generated due to the corresponding bits set in HCINTn. |
RW | 0x0 | ||||||
| 3 | stallmsk | STALL Response Received Interrupt Mask (StallMsk) In scatter/gather DMA mode for host, interrupts will not be generated due to the corresponding bits set in HCINTn. |
RW | 0x0 | ||||||
| 2 | ahberrmsk | AHB Error Mask (AHBErrMsk) In scatter/gather DMA mode for host, interrupts will not be generated due to the corresponding bits set in HCINTn.
|
RW | 0x0 | ||||||
| 1 | chhltdmsk | Channel Halted Mask (ChHltdMsk)
|
RW | 0x0 | ||||||
| 0 | xfercomplmsk | Transfer Completed Mask (XferComplMsk)
|
RW | 0x0 |