hcchar8

         Host Channel 8 Characteristics Register

Module Instance	Base Address	Register Address
`i_usbotg_0_hostgrp`	`0xFFB00400`	`0xFFB00600`
`i_usbotg_1_hostgrp`	`0xFFB40400`	`0xFFB40600`

Offset: 0x200

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`chena` `RW 0x0`	`chdis` `RW 0x0`	`oddfrm` `RW 0x0`	`devaddr` `RW 0x0`							`ec` `RW 0x0`		`eptype` `RW 0x0`		`lspddev` `RW 0x0`	`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`epdir` `RW 0x0`	`epnum` `RW 0x0`				`mps` `RW 0x0`

hcchar8 Fields

Bit

Name

Description

Access

Reset

chena

Channel Enable (ChEna)
When Scatter/Gather mode is enabled 
1'b0: Indicates that the descriptor structure is not yet ready. 
1'b1:  Indicates  that  the  descriptor  structure  and  data  buffer  with 
data is setup and this channel can access the descriptor. 
 
When Scatter/Gather mode is disabled 
This field is set by the application and cleared by the OTG host.  
1'b0: Channel disabled  
1'b1: Channel enabled

Value	Description
0x0	INACTIVE
0x1	ACTIVE

RW

0x0

chdis

Channel Disable (ChDis)
The application sets this bit to stop transmitting/receiving data
on a channel, even before the transfer For that channel is
complete. The application must wait For the Channel Disabled
interrupt before treating the channel as disabled.

Value	Description
0x0	INACTIVE
0x1	ACTIVE

RW

0x0

oddfrm

Odd Frame (OddFrm)
This field is set (reset) by the application to indicate that the OTG host must perform 
a transfer in an odd (micro)frame. This field is applicable for only periodic 
(isochronous and interrupt) transactions.
    1'b0: Even (micro)frame
    1'b1: Odd (micro)frame

RW

0x0

28:22

devaddr

Device Address (DevAddr)
This field selects the specific device serving as the data source
or sink.

RW

0x0

21:20

ec

Multi Count (MC) / Error Count (EC)
When the Split Enable bit of the Host Channel-n Split Control
register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates to
the host the number of transactions that must be executed per
microframe For this periodic endpoint. For non periodic transfers,
this field is used only in DMA mode, and specifies the number
packets to be fetched For this channel before the internal DMA
engine changes arbitration.
 2'b00: Reserved This field yields undefined results.
 2'b01: 1 transaction
 2'b10: 2 transactions to be issued For this endpoint per
microframe
 2'b11: 3 transactions to be issued For this endpoint per
microframe
When HCSPLTn.SpltEna is Set (1'b1), this field indicates the
number of immediate retries to be performed For a periodic split
transactions on transaction errors. This field must be Set to at
least 2'b01.

Value	Description
0x0	RESERVED
0x1	TRANSONE
0x2	TRANSTWO
0x3	TRANSTHREE

RW

0x0

19:18

eptype

Endpoint Type (EPType)
Indicates the transfer type selected.
 2'b00: Control
 2'b01: Isochronous
 2'b10: Bulk
 2'b11: Interrupt

Value	Description
0x0	CTRL
0x1	ISOC
0x2	BULK
0x3	INTERR

RW

0x0

lspddev

Low-Speed Device (LSpdDev)
This field is Set by the application to indicate that this channel is
communicating to a low-speed device.

Value	Description
0x0	DISABLED
0x1	ENABLED

RW

0x0

epdir

Endpoint Direction (EPDir)
Indicates whether the transaction is IN or OUT.
 1'b0: OUT
 1'b1: IN

Value	Description
0x0	OUT
0x1	IN

RW

0x0

14:11

epnum

Endpoint Number (EPNum)
Indicates the endpoint number on the device serving as the data
source or sink.

Value	Description
0xa	ENDPT10
0xb	ENDPT11
0xc	ENDPT12
0xd	ENDPT13
0xe	ENDPT14
0xf	ENDPT15
0x0	ENDPT0
0x1	ENDPT1
0x2	ENDPT2
0x3	ENDPT3
0x4	ENDPT4
0x5	ENDPT5
0x6	ENDPT6
0x7	ENDPT7
0x8	ENDPT8
0x9	ENDPT9

RW

0x0

10:0

mps

Maximum Packet Size (MPS)
Indicates the maximum packet size of the associated endpoint.

RW

0x0