gdfifocfg

         Global DFIFO Configuration Register

Module Instance	Base Address	Register Address
`i_usbotg_0_globgrp`	`0xFFB00000`	`0xFFB0005C`
`i_usbotg_1_globgrp`	`0xFFB40000`	`0xFFB4005C`

Offset: 0x5C

Access: RW

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`epinfobaseaddr` `RW 0x1F80`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`gdfifocfg` `RW 0x2000`

gdfifocfg Fields

Bit	Name	Description	Access	Reset
31:16	`epinfobaseaddr`	EPInfoBaseAddr This field provides the start address of the EP info controller.	`RW`	`0x1F80`
15:0	`gdfifocfg`	GDFIFOCfg This field is for dynamic programming of the DFIFO Size. This value takes effect only when the application programs a non zero value to this register. The value programmed must conform to the guidelines described in 'FIFO RAM Allocation'. The DWC_otg core does not have any corrective logic if the FIFO sizes are programmed incorrectly.	`RW`	`0x2000`

Bit

Name

Description

Access

Reset

31:16

epinfobaseaddr

  EPInfoBaseAddr	
	This field provides the start address of the EP info controller.

RW

0x1F80

15:0

gdfifocfg

	GDFIFOCfg
	This field is for dynamic programming of the DFIFO Size. This value takes effect
only when the application programs a non zero value to this register. The
value programmed must conform to the guidelines described in 'FIFO RAM
Allocation'. The DWC_otg core does not have any corrective logic
if the FIFO sizes are programmed incorrectly.

RW

0x2000