ghwcfg4

         User HW Config4 Register

Module Instance	Base Address	Register Address
`i_usbotg_0_globgrp`	`0xFFB00000`	`0xFFB00050`
`i_usbotg_1_globgrp`	`0xFFB40000`	`0xFFB40050`

Offset: 0x50

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`dma` `RO 0x1`	`dma_configuration` `RO 0x1`	`ineps` `RO 0xF`				`dedfifomode` `RO 0x1`	`sessendfltr` `RO 0x0`	`bvalidfltr` `RO 0x0`	`avalidfltr` `RO 0x0`	`vbusvalidfltr` `RO 0x0`	`iddgfltr` `RO 0x0`	`numctleps` `RO 0xF`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`phydatawidth` `RO 0x0`		`Reserved`						`extendedhibernation` `RO 0x0`	`hibernation` `RO 0x0`	`ahbfreq` `RO 0x1`	`partialpwrdn` `RO 0x0`	`numdevperioeps` `RO 0x0`

ghwcfg4 Fields

Bit

Name

Description

Access

Reset

dma

Scatter/Gather DMA configuration
 1'b0: Non Dynamic configuration
 1'b1: Dynamic configuration

Value	Description
0x1	ENABLED

RO

0x1

dma_configuration

Scatter/Gather DMA configuration
 1'b0: Non-Scatter/Gather DMA configuration
 1'b1: Scatter/Gather DMA configuration

Value	Description
0x0	NONSCATTER
0x1	SCATTER

RO

0x1

29:26

ineps

Number of Device Mode IN Endpoints Including Control
Endpoints (INEps)
Range 0 -15
 0 : 1 IN Endpoint
 1 : 2 IN Endpoints
 ....
15 : 16 IN Endpoints

Value	Description
0xa	ENDPT11
0xb	ENDPT12
0xc	ENDPT13
0xd	ENDPT14
0xe	ENDPT15
0xf	ENDPT16
0x0	ENDPT1
0x1	ENDPT2
0x2	ENDPT3
0x3	ENDPT4
0x4	ENDPT5
0x5	ENDPT6
0x6	ENDPT7
0x7	ENDPT8
0x8	ENDPT9
0x9	ENDPT10

RO

0xF

dedfifomode

Enable Dedicated Transmit FIFO For device IN Endpoints
(DedFifoMode)
 1'b0 : Dedicated Transmit FIFO Operation not enabled.
 1'b1 : Dedicated Transmit FIFO Operation enabled.

Value	Description
0x1	ENABLED

RO

0x1

sessendfltr

session_end Filter Enabled (SessEndFltr)
 1'b0: No filter
 1'b1: Filter

Value	Description
0x0	DISABLED

RO

0x0

bvalidfltr

b_valid Filter Enabled (BValidFltr)
 1'b0: No filter
 1'b1: Filter

Value	Description
0x0	DISABLED

RO

0x0

avalidfltr

a_valid Filter Enabled (AValidFltr)
 1'b0: No filter
 1'b1: Filter

Value	Description
0x0	DISABLED

RO

0x0

vbusvalidfltr

VBUS Valid Filter Enabled (VBusValidFltr)
 1'b0: No filter
 1'b1: Filter

Value	Description
0x0	DISABLED

RO

0x0

iddgfltr

IDDIG Filter Enable (IddgFltr)
 1'b0: No filter
 1'b1: Filter

Value	Description
0x0	DISABLED

RO

0x0

19:16

numctleps

Number of Device Mode Control Endpoints in Addition to
Endpoint 0 (NumCtlEps)
Range: 0-15

Value	Description
0xa	ENDPT10
0xb	ENDPT11
0xc	ENDPT12
0xd	ENDPT13
0xe	ENDPT14
0xf	ENDPT15
0x0	ENDPT0
0x1	ENDPT1
0x2	ENDPT2
0x3	ENDPT3
0x4	ENDPT4
0x5	ENDPT5
0x6	ENDPT6
0x7	ENDPT7
0x8	ENDPT8
0x9	ENDPT9

RO

0xF

15:14

phydatawidth

UTMI+ PHY/ULPI-to-Internal UTMI+ Wrapper Data Width
(PhyDataWidth)
When a ULPI PHY is used, an internal wrapper converts ULPI to
UTMI+ .
 2'b00: 8 bits
 2'b01: 16 bits
 2'b10: 8/16 bits, software selectable
 Others: Reserved

RO

0x0

extendedhibernation

Enable Hibernation
 1'b0: Extended Hibernation feature not enabled
 1'b1: Extended Hibernation feature enabled

RO

0x0

hibernation

Enable Hibernation (Hibernation)
 1'b0: Hibernation feature not enabled
 1'b1: Hibernation feature enabled

Value	Description
0x0	DISABLED

RO

0x0

ahbfreq

Minimum AHB Frequency Less Than 60 MHz (AhbFreq)
 1'b0: No
 1'b1: Yes

Value	Description
0x1	ENABLED

RO

0x1

partialpwrdn

Enable Partial Power Down (PartialPwrDn)
 1'b0: Partial Power Down Not Enabled
 1'b1: Partial Power Down Enabled

Value	Description
0x0	DISABLED

RO

0x0

3:0

numdevperioeps

Number of Device Mode Periodic IN Endpoints
(NumDevPerioEps)
Range: 0-15

RO

0x0