ghwcfg3
User HW Config3 Register
| Module Instance | Base Address | Register Address |
|---|---|---|
| i_usbotg_0_globgrp | 0xFFB00000 | 0xFFB0004C |
| i_usbotg_1_globgrp | 0xFFB40000 | 0xFFB4004C |
Offset: 0x4C
Access: RO
Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
dfifodepth RO 0x1F80 |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
lpmmode RO 0x0 |
bcsupport RO 0x0 |
hsicmode RO 0x0 |
adpsupport RO 0x0 |
rsttype RO 0x0 |
optfeature RO 0x0 |
vndctlsupt RO 0x1 |
i2cintsel RO 0x0 |
otgen RO 0x1 |
pktsizewidth RO 0x6 |
xfersizewidth RO 0x8 |
|||||
ghwcfg3 Fields
| Bit | Name | Description | Access | Reset | ||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31:16 | dfifodepth | DFIFO Depth (DfifoDepth - EP_LOC_CNT) This value is in terms of 32-bit words. Minimum value is 32 Maximum value is 32,768 |
RO | 0x1F80 | ||||||||||||||||||||
| 15 | lpmmode | LPM mode specified for Mode of Operation.
|
RO | 0x0 | ||||||||||||||||||||
| 14 | bcsupport | This bit indicates the HS OTG controller support for Battery Charger. 0 - No Battery Charger Support 1 - Battery Charger support present.
|
RO | 0x0 | ||||||||||||||||||||
| 13 | hsicmode | HSIC mode specified for Mode of Operation Value Range: 0 - 1 1: HSIC-capable with shared UTMI PHY interface 0: Non-HSIC-capable
|
RO | 0x0 | ||||||||||||||||||||
| 12 | adpsupport | This bit indicates whether ADP logic is present within or external to the HS OTG controller 0: No ADP logic present with HSOTG controller 1: ADP logic is present along with HSOTG controller.
|
RO | 0x0 | ||||||||||||||||||||
| 11 | rsttype | Reset Style For Clocked always Blocks in RTL (RstType) 1'b0: Asynchronous reset is used in the core 1'b1: Synchronous reset is used in the core
|
RO | 0x0 | ||||||||||||||||||||
| 10 | optfeature | Optional Features Removed (OptFeature) Indicates whether the User ID register, GPIO interface ports, and SOF toggle and counter ports were removed For gate count optimization by enabling Remove Optional Features. 1'b0: No 1'b1: Yes
|
RO | 0x0 | ||||||||||||||||||||
| 9 | vndctlsupt | Vendor Control Interface Support (VndctlSupt) 1'b0: Vendor Control Interface is not available on the core. 1'b1: Vendor Control Interface is available.
|
RO | 0x1 | ||||||||||||||||||||
| 8 | i2cintsel | I2C Selection (I2CIntSel) 1'b0: I2C Interface is not available on the core. 1'b1: I2C Interface is available on the core.
|
RO | 0x0 | ||||||||||||||||||||
| 7 | otgen | OTG Function Enabled (OtgEn) The application uses this bit to indicate the DWC_otg core's OTG capabilities. 1'b0: Not OTG capable 1'b1: OTG Capable
|
RO | 0x1 | ||||||||||||||||||||
| 6:4 | pktsizewidth | Width of Packet Size Counters (PktSizeWidth) 3'b000: 4 bits 3'b001: 5 bits 3'b010: 6 bits 3'b011: 7 bits 3'b100: 8 bits 3'b101: 9 bits 3'b110: 10 bits Others: Reserved
|
RO | 0x6 | ||||||||||||||||||||
| 3:0 | xfersizewidth | Width of Transfer Size Counters (XferSizeWidth) 4'b0000: 11 bits 4'b0001: 12 bits ... 4'b1000: 19 bits Others: Reserved
|
RO | 0x8 |