ghwcfg2

         User HW Config2 Register
Module Instance Base Address Register Address
i_usbotg_0_globgrp 0xFFB00000 0xFFB00048
i_usbotg_1_globgrp 0xFFB40000 0xFFB40048

Offset: 0x48

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

tknqdepth

RO 0x8

ptxqdepth

RO 0x0

nptxqdepth

RO 0x2

Reserved

multiprocintrpt

RO 0x0

dynfifosizing

RO 0x1

periosupport

RO 0x1

numhstchnl

RO 0xF
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

numhstchnl

RO 0xF

numdeveps

RO 0xF

fsphytype

RO 0x0

hsphytype

RO 0x2

singpnt

RO 0x0

otgarch

RO 0x2

otgmode

RO 0x0

ghwcfg2 Fields

Bit Name Description Access Reset
30:26 tknqdepth 
Device Mode IN Token Sequence Learning Queue Depth
(TknQDepth)
Range: 0-30
RO 0x8
25:24 ptxqdepth 
Host Mode Periodic Request Queue Depth (PTxQDepth)
 2'b00: 2
 2'b01: 4
 2'b10: 8
 2'b11:16
Value Description
0x0 QUE2
0x1 QUE4
0x2 QUE8
0x3 QUE16
RO 0x0
23:22 nptxqdepth 
Non-periodic Request Queue Depth (NPTxQDepth)
 2'b00: 2
 2'b01: 4
 2'b10: 8
 Others: Reserved
Value Description
0x0 TWO
0x1 FOUR
0x2 EIGHT
RO 0x2
20 multiprocintrpt 
Multi Processor Interrupt Enabled (MultiProcIntrpt)
 1'b0: No
 1'b1: Yes
Value Description
0x0 DISABLED
RO 0x0
19 dynfifosizing 
Dynamic FIFO Sizing Enabled (DynFifoSizing)
 1'b0: No
 1'b1: Yes
Value Description
0x1 ENABLED
RO 0x1
18 periosupport 
Periodic OUT Channels Supported in Host Mode (PerioSupport)
 1'b0: No
 1'b1: Yes
Value Description
0x1 ENABLED
RO 0x1
17:14 numhstchnl 
Number of Host Channels (NumHstChnl)
Indicates the number of host channels supported by the core in
Host mode. The range of this field is 0-15: 0 specifies 1 channel,
15 specifies 16 channels.
Value Description
0xa HOSTCH10
0xb HOSTCH11
0xc HOSTCH12
0xd HOSTCH13
0xe HOSTCH14
0xf HOSTCH15
0x0 HOSTCH0
0x1 HOSTCH1
0x2 HOSTCH2
0x3 HOSTCH3
0x4 HOSTCH4
0x5 HOSTCH5
0x6 HOSTCH6
0x7 HOSTCH7
0x8 HOSTCH8
0x9 HOSTCH9
RO 0xF
13:10 numdeveps 
Number of Device Endpoints (NumDevEps)
Indicates the number of device endpoints supported by the core
in Device mode in addition to control endpoint 0. The range of
this field is 1-15.
Value Description
0xa ENDPT10
0xb ENDPT11
0xc ENDPT12
0xd ENDPT13
0xe ENDPT14
0xf ENDPT15
0x0 ENDPT0
0x1 ENDPT1
0x2 ENDPT2
0x3 ENDPT3
0x4 ENDPT4
0x5 ENDPT5
0x6 ENDPT6
0x7 ENDPT7
0x8 ENDPT8
0x9 ENDPT9
RO 0xF
9:8 fsphytype 
Full-Speed PHY Interface Type (FSPhyType)
 2'b00: Full-speed interface not supported
 2'b01: Dedicated full-speed interface
 2'b10: FS pins shared with UTMI+ pins
 2'b11: FS pins shared with ULPI pins
Value Description
0x2 FULLSPEED
RO 0x0
7:6 hsphytype 
High-Speed PHY Interface Type (HSPhyType)
 2'b00: High-Speed interface not supported
 2'b01: UTMI+
 2'b10: ULPI
 2'b11: UTMI+ and ULPI
Value Description
0x0 NOHS
0x2 ULPI
RO 0x2
5 singpnt 
Point-to-Point (SingPnt)
 1'b0: Multi-point application  (hub and split support)
 1'b1: Single-point application (no hub and split support)
Value Description
0x1 SINGLEPOINT
RO 0x0
4:3 otgarch 
Architecture (OtgArch)
 2'b00: Slave-Only
 2'b01: External DMA
 2'b10: Internal DMA
 Others: Reserved
Value Description
0x2 DMAMODE
RO 0x2
2:0 otgmode 
Mode of Operation (OtgMode)
 3'b000: HNP- and SRP-Capable OTG (Host & Device)
 3'b001: SRP-Capable OTG (Host & Device)
 3'b010: Non-HNP and Non-SRP Capable OTG (Host &
Device)
 3'b011: SRP-Capable Device
 3'b100: Non-OTG Device
 3'b101: SRP-Capable Host
 3'b110: Non-OTG Host
 Others: Reserved
Value Description
0x0 HNPSRP
0x1 SRPOTG
0x2 NHNPNSRP
0x3 SRPCAPD
0x4 NONOTGD
0x5 SRPCAPH
0x6 NONOTGH
RO 0x0