ECC_wdctrl

         Bits to Enable/Disable Watch Dog Timer

Module Instance	Base Address	Register Address
`ecc_otg0_ecc_registerBlock`	`0xFF8C8800`	`0xFF8C8880`
`ecc_otg1_ecc_registerBlock`	`0xFF8C8C00`	`0xFF8C8C80`

Offset: 0x80

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`															`WDEN_RAM` `0x0`

ECC_wdctrl Fields

Bit	Name	Description	Access	Reset
0	`WDEN_RAM`	Enable watchdog timeout for OCP register access to IP RAM.	`RW`	`0x0`