CTRL

         ECC Control Register

Module Instance	Base Address	Register Address
`ecc_sdmmc_ecc_registerBlock`	`0xFF8C2C00`	`0xFF8C2C08`

Offset: 0x8

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`							`INITB` `0x0`	`Reserved`							`INITA` `0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`						`CNT_RSTB` `0x0`	`CNT_RSTA` `0x0`	`Reserved`							`ECC_EN` `0x0`

CTRL Fields

Bit	Name	Description	Access	Reset
24	`INITB`	Enable for the hardware memory initialization PORTB.	`RW`	`0x0`
16	`INITA`	Enable for the hardware memory initialization PORTA.	`RW`	`0x0`
9	`CNT_RSTB`	Enable to reset internal single-bit error counter B value to zero	`RW`	`0x0`
8	`CNT_RSTA`	Enable to reset internal single-bit error counter A value to zero	`RW`	`0x0`
0	`ECC_EN`	Enable for the ECC detection and correction logic.	`RW`	`0x0`