ERRINTENR

         Error Interrupt reset.

Module Instance	Base Address	Register Address
`ecc_emac0_tx_ecc_registerBlock`	`0xFF8C0C00`	`0xFF8C0C18`
`ecc_emac1_tx_ecc_registerBlock`	`0xFF8C1400`	`0xFF8C1418`
`ecc_emac2_tx_ecc_registerBlock`	`0xFF8C1C00`	`0xFF8C1C18`

Offset: 0x18

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`															`SERRINTR` `0x0`

ERRINTENR Fields

Bit	Name	Description	Access	Reset
0	`SERRINTR`	This bit is used to reset the single-bit error interrupt bit. Reads reflect SERRINTEN. 1’b0: Writing of zero has no effect. 1’b1: By writing one, this bit will reset SERRINTEN bit to 0. This is performing a bitwise writing of this feature.	`RW`	`0x0`

Bit

Name

Description

Access

Reset

SERRINTR

This bit is used to reset the single-bit error interrupt bit. Reads reflect SERRINTEN.
1’b0: Writing of zero has no effect.
1’b1: By writing one, this bit will reset SERRINTEN bit to 0. This is performing a bitwise writing of this feature.

RW

0x0