SMMU_CB0_TTBR0_high

         The Translation Table Base register 0 holds the base address of the translation table 0.
      
Note: For register and programming information, please refer to the ARM CoreLink MMU System Memory Management Unit Technical Reference Manual.
Module Instance Base Address Register Address
i_aps_smmu_secure_registers 0xFA000000 0xFA020024

Size: 32

Offset: 0x20024

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

ASID

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

address

RW 0x0