MPFE_HMCA_SPARE1

         spare configuration register

Module Instance	Base Address	Register Address
`soc_hmc_adp_csr_inst_0_ocp_slv_block`	`0xF8011000`	`0xF80110E0`

Size: 32

Offset: 0xE0

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`													`CFG_0` `0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`CFG_1` `0x0`		`CFG_2` `0x0`				`CFG_3` `0x0`					`CFG_4` `0x0`

MPFE_HMCA_SPARE1 Fields

Bit	Name	Description	Access	Reset
18:16	`CFG_0`	spare	`RW`	`0x0`
15:14	`CFG_1`	spare	`RW`	`0x0`
13:10	`CFG_2`		`RW`	`0x0`
9:5	`CFG_3`	spare	`RW`	`0x0`
4:0	`CFG_4`	spare	`RW`	`0x0`