MSR

         Modem Status Register
It should be noted that whenever bits 0, 1, 2 or 3 is set to logic one, to indicate
a change on the modem control inputs, a modem status interrupt will be generated
if enabled via the IER regardless of when the change occurred. Since the delta bits
(bits 0, 1, 3) can get set after a reset if their respective modem signals are
active (see individual bits for details), a read of the MSR after reset can be
performed to prevent unwanted interrupts.
      
Module Instance Base Address Register Address
i_uart_0_uart_address_block 0xFFC02000 0xFFC02018
i_uart_1_uart_address_block 0xFFC02100 0xFFC02118

Size: 32

Offset: 0x18

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RSVD_MSR_31to8

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RSVD_MSR_31to8

RO 0x0

DCD

RO 0x0

RI

RO 0x0

DSR

RO 0x0

CTS

RO 0x0

DDCD

RO 0x0

TERI

RO 0x0

DDSR

RO 0x0

DCTS

RO 0x0

MSR Fields

Bit Name Description Access Reset
31:8 RSVD_MSR_31to8
Reserved bits [31:8] - Read Only
RO 0x0
7 DCD
Data Carrier Detect.
This is used to indicate the current state of the modem control line dcd_n. That is
this bit is the complement dcd_n. When the Data Carrier Detect input (dcd_n) is
asserted it is an indication that the carrier has been detected by the modem or
data set.
0 = dcd_n input is de-asserted (logic 1)
1 = dcd_n input is asserted (logic 0)
In Loopback Mode (MCR[4] set to one), DCD is the same as MCR[3] (Out2).
Value Description
0x0 dcd_n input is de-asserted (logic 1)
0x1 dcd_n input is asserted (logic 0)
RO 0x0
6 RI
Ring Indicator.
This is used to indicate the current state of the modem control line ri_n. That is
this bit is the complement ri_n. When the Ring Indicator input (ri_n) is asserted
it is an indication that a telephone ringing signal has been received by the modem
or data set.
0 = ri_n input is de-asserted (logic 1)
1 = ri_n input is asserted (logic 0)
In Loopback Mode (MCR[4] set to one), RI is the same as MCR[2] (Out1).
Value Description
0x0 ri_n input is de-asserted (logic 1)
0x1 ri_n input is asserted (logic 0)
RO 0x0
5 DSR
Data Set Ready.
This is used to indicate the current state of the modem control line dsr_n. That is
this bit is the complement dsr_n. When the Data Set Ready input (dsr_n) is asserted
it is an indication that the modem or data set is ready to establish communications
with the DW_apb_uart.
0 = dsr_n input is de-asserted (logic 1)
1 = dsr_n input is asserted (logic 0)
In Loopback Mode (MCR[4] set to one), DSR is the same as MCR[0] (DTR).
Value Description
0x0 dsr_n input is de-asserted (logic 1)
0x1 dsr_n input is asserted (logic 0)
RO 0x0
4 CTS
Clear to Send.
This is used to indicate the current state of the modem control line cts_n. That is,
this bit is the complement cts_n. When the Clear to Send input (cts_n) is asserted
it is an indication that the modem or data set is ready to exchange data with the
DW_apb_uart.
0 = cts_n input is de-asserted (logic 1)
1 = cts_n input is asserted (logic 0)
In Loopback Mode (MCR[4] set to one), CTS is the same as MCR[1] (RTS).
Value Description
0x0 cts_n input is de-asserted (logic 1)
0x1 cts_n input is asserted (logic 0)
RO 0x0
3 DDCD
Delta Data Carrier Detect.
This is used to indicate that the modem control line dcd_n has changed since the last
time the MSR was read. That is:
0 = no change on dcd_n since last read of MSR
1 = change on dcd_n since last read of MSR
Reading the MSR clears the DDCD bit.
In Loopback Mode (MCR[4] set to one), DDCD reflects changes on MCR[3] (Out2).
Note, if the DDCD bit is not set and the dcd_n signal is asserted (low) and a reset
occurs (software or otherwise), then the DDCD bit will get set when the reset is
removed if the dcd_n signal remains asserted.
Value Description
0x0 No change on dcd_n since last read of MSR
0x1 change on dcd_n since last read of MSR
RO 0x0
2 TERI
Trailing Edge of Ring Indicator.
This is used to indicate that a change on the input ri_n (from an active low, to
an inactive high state) has occurred since the last time the MSR was read. That is:
0 = no change on ri_n since last read of MSR
1 = change on ri_n since last read of MSR
Reading the MSR clears the TERI bit.
In Loopback Mode (MCR[4] set to one), TERI reflects when MCR[2] (Out1) has changed
state from a high to a low.
Value Description
0x0 No change on ri_n since last read of MSR
0x1 change on ri_n since last read of MSR
RO 0x0
1 DDSR
Delta Data Set Ready.
This is used to indicate that the modem control line dsr_n has changed since
the last time the MSR was read. That is:
0 = no change on dsr_n since last read of MSR
1 = change on dsr_n since last read of MSR
Reading the MSR clears the DDSR bit.
In Loopback Mode (MCR[4] set to one), DDSR reflects changes on MCR[0] (DTR).
Note, if the DDSR bit is not set and the dsr_n signal is asserted (low) and a reset
occurs (software or otherwise), then the DDSR bit will get set when the reset is
removed if the dsr_n signal remains asserted.
Value Description
0x0 No change on dsr_n since last read of MSR
0x1 change on dsr_n since last read of MSR
RO 0x0
0 DCTS
Delta Clear to Send.
This is used to indicate that the modem control line cts_n has changed since the
last time the MSR was read. That is:
0 = no change on cts_n since last read of MSR
1 = change on cts_n since last read of MSR
Reading the MSR clears the DCTS bit.
In Loopback Mode (MCR[4] set to one), DCTS reflects changes on MCR[1] (RTS).
Note, if the DCTS bit is not set and the cts_n signal is asserted (low) and a reset
occurs (software or otherwise), then the DCTS bit will get set when the reset is
removed if the cts_n signal remains asserted.
Value Description
0x0 No change on cts_n since last read of MSR
0x1 change on cts_n since last read of MSR
RO 0x0