sdmmc 

         Registers used by the SDMMC Controller. All fields are reset by a cold or warm reset.
Module Instance Base Address Register Address
i_sys_mgr_core 0xFFD12000 0xFFD12028

Size: 32

Offset: 0x28

Access: RW

Access mode: PRIVILEGEMODE | SECURE

Note: The processor must make a secure, privileged bus access to this register. You can configure processor mode settings in the control registers of the ARM Cortex-A53 MPcore processor. For more information about processor modes, please refer to the ARM Infocenter.

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

smplsel

RW 0x0

Reserved

drvsel

RW 0x0

sdmmc Fields

Bit Name Description Access Reset
6:4 smplsel 
Select which phase shift of the clock for cclk_in_sample.
Value Description
0 degrees0
1 degrees45
2 degrees90
3 degrees135
4 degrees180
5 degrees225
6 degrees270
7 degrees315
RW 0x0
2:0 drvsel 
Select which phase shift of the clock for cclk_in_drv.
Value Description
0 degrees0
1 degrees45
2 degrees90
3 degrees135
4 degrees180
5 degrees225
6 degrees270
7 degrees315
RW 0x0