fpga2sdram_manager_main_SidebandManager Address Map

Module Instance	Base Address	End Address
`soc_mpfe_noc_inst_0_fpga2sdram_manager_main_SidebandManager`	`0xF8024000`	`0xF80240FF`

Register	Offset	Width	Access	Reset Value	Description
`fpga2sdram_manager_main_SidebandManager_Id_CoreId`	`0x0`	`32`	`RO`	`0x4E344C0B`
`fpga2sdram_manager_main_SidebandManager_Id_RevisionId`	`0x4`	`32`	`RO`	`0x56C01000`
`fpga2sdram_manager_main_SidebandManager_FaultEn`	`0x8`	`32`	`RW`	`0x00000000`
`fpga2sdram_manager_main_SidebandManager_FaultStatus`	`0xC`	`32`	`RO`	`0x00000000`
`fpga2sdram_manager_main_SidebandManager_FlagInEn0`	`0x10`	`32`	`RW`	`0x00000000`
`fpga2sdram_manager_main_SidebandManager_FlagInStatus0`	`0x14`	`32`	`RO`	`0x00000000`
`fpga2sdram_manager_main_SidebandManager_FlagOutSet0`	`0x50`	`32`	`RW`	`0x00000000`	To set, write 1 to FlagOutSet0 Note: This register is only used for set, not for clear.
`fpga2sdram_manager_main_SidebandManager_FlagOutClr0`	`0x54`	`32`	`RW`	`0x00000000`	To clear, write 1 to FlagOutClr0
`fpga2sdram_manager_main_SidebandManager_FlagOutStatus0`	`0x58`	`32`	`RO`	`0x00000000`