IC_SLV_DATA_NACK_ONLY

         Name: Generate Slave Data NACK Register
Size: 1 bit
Address Offset: 0x84
Read/Write Access: Read/Write
The register is used to generate a NACK for
the data part of a transfer when DW_apb_i2c is
acting as a slave-receiver. This register only
exists when the IC_SLV_DATA_NACK_ONLY parameter
is set to 1. When this parameter disabled, this
register does not exist and writing to the register's
address has no effect.
Dependencies: This register is not applicable  when IC_ULTRA_FAST_MODE=1

      
Module Instance Base Address Register Address
i_i2c_emac_0_DW_apb_i2c_addr_block1 0xFFC02A00 0xFFC02A84
i_i2c_emac_1_DW_apb_i2c_addr_block1 0xFFC02B00 0xFFC02B84
i_i2c_emac_2_DW_apb_i2c_addr_block1 0xFFC02C00 0xFFC02C84

Size: 32

Offset: 0x84

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RSVD_IC_SLV_DATA_NACK_ONLY

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RSVD_IC_SLV_DATA_NACK_ONLY

RO 0x0

NACK

RW 0x0

IC_SLV_DATA_NACK_ONLY Fields

Bit Name Description Access Reset
31:1 RSVD_IC_SLV_DATA_NACK_ONLY
Reserved bits - Read Only
RO 0x0
0 NACK
Generate NACK.
This NACK generation only occurs when DW_apb_i2c is a
slave-receiver. If this register is set to a value of 1,
it can only generate a NACK after a data byte is received;
hence, the data transfer is aborted and the data received
is not pushed to the receive buffer.
When the register is set to a value of 0, it generates
NACK/ACK, depending on normal criteria.
1 = generate NACK after data byte received
0 = generate NACK/ACK normally
Reset value: 0x0
Value Description
0x0 Slave reciever generates NACK normally
0x1 Slave reciever generates NACK upon data reception only
RW 0x0