chip_interleave_enable_and_allow_int_reads

         
      
Module Instance Base Address Register Address
sdm_i_nand_dma 0xFFA10700 0xFFA10780

Size: 32

Offset: 0x80

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

cmd_dma_error_enable

RW 0x1

Reserved

allow_int_reads_within_luns

RW 0x1

Reserved

chip_interleave_enable

RW 0x0

chip_interleave_enable_and_allow_int_reads Fields

Bit Name Description Access Reset
8 cmd_dma_error_enable
This bit informs the CDMA channels to stop working on any new MAP10 Command DMAcommands from the host after encountering an
                 error situation till the error bit for that corresponding channel is cleared in the cmd_dma_channel_error register by f/w.
                 When the CDMA channel encounters an error, it will set the corresponding error bit in cmd_dma_channel_error register
                 If this bit is set, the channel will stop executing any further commands 
                 till f/w comes and clears the error bit in the cmd_dma_channel_error_register.
                 If this bit is not set, controller will still keep on executing new commands issued from f/w.
RW 0x1
4 allow_int_reads_within_luns
This bit informs the controller to enable or disable simultaneous read accesses
                  to different LUNS in the same bank. This bit is of importance only if the controller
                  supports interleaved operations among LUNs and if the device has multiple LUNS.
                  If the bit is disabled, the controller will send read commands to different LUNS of 
                  of the same bank only sequentially and if enabled, the controller will issue simultaneous
                  read accesses to LUNS of same bank if required.
                  [list][*]1 - Enable  [*]0 - Disable[/list] 
RW 0x1
0 chip_interleave_enable
This bit informs the controller to enable or disable interleaving
                  among banks/LUNS to increase the net performance of the controller. 
                  [list][*]1 - Enable interleaving  [*]0 - Disable Interleaving[/list] 
RW 0x0