EMMC_DDR_REG

         
Name: EMMC DDR Register
Size: 32 bits
Address Offset: 0x10C
Read/Write access: read/write
      
Module Instance Base Address Register Address
i_sdmmc_sdmmc_block_1 0xFF8D1000 0xFF8D110C

Size: 32

Offset: 0x10C

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

HS400_MODE

RO 0x0

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

HALF_START_BIT_0

RW 0x0

EMMC_DDR_REG Fields

Bit Name Description Access Reset
31 HS400_MODE
HS400 Mode Enable
                                                 ■ 1'b0 - Disable
                                                 ■ 1'b1 - Enable
Note: The application is required to set this bit to '1' before initiating any data
transfer CMD in HS400 mode. This bit shall be cleared by the host on exiting HS400 mode.
In non HS400 mode, this bit shall be set to '0'
Value Description
0x0 HS400 Mode Disabled
0x1 HS400 Mode Enabled
RO 0x0
0 HALF_START_BIT_0
Control for start bit detection mechanism inside 
DWC_mobile_storage based on duration of start bit; each bit refers to one slot. For eMMC 4.5, start bit can
be:
                                                 ■ Full cycle (HALF_START_BIT = 0)
                                                 ■ Less than one full cycle (HALF_START_BIT = 1)
Set HALF_START_BIT=1 for eMMC 4.5 and above; set to 0 for SD applications.
Note: This bit is not applicable for HS400 mode
Value Description
0x0 HALF_START_BIT disabled
0x1 HALF_START_BIT enabled
RW 0x0